Public sample packet · RTL review compression

Ark Axiom Review Packet: Public Amaranth HDL GPU Core

A bounded review-compression packet for WarpCore. Not verification, not a correctness proof, not FPGA readiness, and not ASIC readiness. The packet shows what a senior hardware reviewer should inspect first.

Open packet JSON Run receipt Claims boundary

Files in local source snapshot

Ranked review targets

PASS

C++ simulator tests · 14 passed

PASS

Shipped Amaranth HDL testbench

Claim boundary

The packet is review compression. Not signoff.

Ark Axiom ran a bounded pass over the public local source snapshot to produce ranked review targets, evidence links, blocked claims, human-review questions, and a run receipt.

Allowed: Ark Axiom generated a bounded RTL review-compression packet; shipped simulator tests passed; shipped HDL testbench passed; Verilog generation succeeded locally.

Blocked: WarpCore verified, GPU correctness proven, formal proof complete, FPGA ready, ASIC ready, synthesis signoff complete, simulator/HDL equivalence proven.

{
  "packet_authorizes_execution": false,
  "human_operator_handoff": true,
  "packet_type": "ark_axiom_rtl_review_compression_packet"
}

Top review targets

What a hardware reviewer should inspect first.

The packet compressed the source, generated RTL, and simulator surfaces into a bounded set of review targets. These are not defect claims. They are the places where senior review has the highest leverage.

Scheduler timing

Stall, halt, countdown, readiness, and current-warp switching interactions.

Human review recommended

SIMT lane execution

The HDL instantiates eight ALUs but the top-level execution path drives `alus[0]` while iterating lanes.

Claim review required

Simulator / HDL ISA parity

The simulator uses a richer RISC-V-like object model while the HDL uses fixed 32-bit encoding.

Parity review required

Memory assumptions

HDL generation uses 4KB data memory; the simulator uses 64KB byte-addressed memory and larger demo addresses.

Boundary review required

LOAD / STORE latency

Review whether memory latency is architectural, cosmetic, or sufficient for the intended implementation.

Latency model review required

Generated Verilog provenance

Verilog regeneration succeeded, but regenerated `gpu_core.v` differs from the downloaded generated artifact.

Diff review required

Run evidence

Executed locally. Still bounded.

Check	Result	Boundary
C++ simulator tests	Passed: 14 passed, 0 failed.	Simulator evidence only; not HDL equivalence.
Amaranth HDL testbench	Passed shipped simple ALU, vector add, and scalar multiply programs.	Shipped demo coverage; not exhaustive verification.
Verilog generation	Generated `alu.v`, `decoder.v`, `scheduler.v`, and `gpu_core.v`.	Generation succeeded; synthesis signoff not performed.
Downloaded vs regenerated RTL	Downloaded `gpu_core.v`: 115,355 bytes. Regenerated: 125,686 bytes.	Provenance diff review required before generated-RTL claims.

Packet files

Replayable artifacts, not self-reported vibes.

The raw packet files are published with hashes so reviewers can inspect the JSON, claims boundary, evidence table, review questions, and run receipt directly.

Machine-readable packet

Scope, ranked targets, allowed claims, blocked claims, and execution authorization boundary.

packet.json ->

Evidence and manifest

Source snapshot counts, key file hashes, regenerated Verilog hashes, and evidence status.

artifact_manifest.json ->
evidence_table.md ->

Review handoff

Ranked targets and exact questions for a hardware reviewer to inspect next.

review_targets.md ->
human_review_questions.md ->

Claim boundary and receipt

Blocked claims, public-safe framing, executed commands, outcomes, and packet hashes.

CLAIMS_BOUNDARY.md ->
run_receipt.md ->
hashes.sha256 ->