# Human Review Questions

1. Is the top-level HDL intended to execute lanes serially through `alus[0]`, or should the eight instantiated ALUs be driven in parallel?
2. Should public copy say "8 lanes" but avoid "8 parallel ALUs" unless the generated RTL actually drives all eight lanes concurrently?
3. Is the standalone `RegisterFile` module authoritative, or is the inline register-file memory inside `GPUCore` the real implementation?
4. Should the HDL and C++ simulator have an explicit ISA mapping table, including unsupported simulator-only operations?
5. Are simulator demo addresses such as `0x1000`, `0x1100`, and `0x2000` intentionally simulator-only given the HDL 4KB data-memory configuration?
6. Does the HDL memory-stall model represent actual memory latency, or does it perform the memory operation before stalling for scheduling demonstration?
7. Are same-cycle stall and halt requests in the scheduler resolved in the intended priority order?
8. Should `HALT` operate per warp only, or should it also interact with lane masks or active masks?
9. Is branch control intentionally lane-0-only for all warps and programs?
10. What negative branch-offset and PC-boundary tests are required before claiming branch support beyond demo coverage?
11. Why does regenerated `gpu_core.v` differ from the downloaded generated `gpu_core.v`, and is the difference explained by toolchain version, stale checked-in output, or source drift?
12. What exact synthesis target, constraints, and top-module assumptions would be needed before any FPGA/ASIC readiness language is allowed?