# Ranked Review Targets

1. HDL scheduler state-transition ordering
2. HDL SIMT lane execution versus eight-ALU claim
3. Simulator versus HDL ISA parity
4. Memory model parity and address-range assumptions
5. LOAD/STORE latency semantics
6. HALT behavior and all-halted detection
7. Register-file integration and address encoding
8. Lane masking and active-thread assumptions
9. Branch semantics and lane-0 decision model
10. Generated Verilog provenance
11. Test coverage claims versus executed evidence
12. Synthesis-script assumptions

Compression result:

- Source snapshot: 43 files
- Python source/test/generation lines: 2,622
- Generated Verilog lines: 4,516
- C++/header/test lines: 1,205
- Review surface compressed to: 12 ranked review targets

Senior-review priority:

The first pass should focus on scheduler timing, lane execution structure, ISA/memory parity, and generated-Verilog provenance. Those are the review surfaces most likely to determine whether public claims and downstream review plans are aligned with the actual artifact.