# Evidence Table

| Evidence surface | Observed support | Packet status |
|---|---|---|
| Public source snapshot | Local folder reviewed at `/Users/zolboon/Downloads/WarpCore-main`; no `.git` metadata present. | Manifest recorded; commit unavailable |
| HDL architecture | `gpu-core/README.md` describes 2 warps, 8 lanes, 16 threads, 4KB data memory, 4-cycle latency, custom 32-bit fixed-width ISA. | Supported as declared documentation |
| HDL top-level implementation | `gpu-core/rtl/gpu_core.py` instantiates scheduler, decoder, ALUs, memories, register file, and FSM. | Review target, not verified |
| Eight-lane execution claim | `gpu-core/rtl/gpu_core.py` instantiates eight ALUs but drives `alus[0]` while iterating `current_lane`. | Claim review required |
| Scheduler | `gpu-core/rtl/scheduler.py` has READY/STALLED/FINISHED states, stall counters, and current-warp switching. | Senior review recommended |
| Register indexing | HDL uses `(current_warp << 8) | (current_lane << 5) | reg`; standalone `regfile.py` uses same conceptual encoding. | Human consistency review recommended |
| Memory latency | LOAD/STORE uses memory then requests scheduler stall after all lanes complete. | Latency semantics review required |
| HDL ISA | `gpu-core/rtl/isa.py` uses 4-bit opcode and fixed 32-bit fields. | Supported as HDL ISA definition |
| Simulator ISA | `gpu-sim/include/isa.h` uses a richer enum/object model with RISC-V-like opcodes and additional instructions. | HDL/sim parity not proven |
| Memory-size parity | HDL generation uses 1024 32-bit words / 4KB; simulator config uses 64KB byte memory. | Boundary mismatch flagged |
| Simulator tests | `make test` executed successfully from scratch copy. Output: 14 passed, 0 failed. | Simulator evidence passed |
| HDL tests | Packet-local virtualenv installed `amaranth==0.5.8` and `amaranth-yosys==0.50.0.0.post124`; `python tb/test_gpu.py` passed simple ALU, vector add, and scalar multiply. | Shipped HDL testbench passed |
| Generated Verilog | `python build/generate_verilog.py` generated `alu.v`, `decoder.v`, `scheduler.v`, and `gpu_core.v`; regenerated `gpu_core.v` hash is `6bedf9bb69c96b9473962dfacdbb1ec58b531bb7bd2cfedfb935a3d6c7b3844c`. | Regeneration passed; diff review required |
| Downloaded vs regenerated Verilog | Downloaded `gpu_core.v` was 115,355 bytes with hash `140257ba...`; regenerated `gpu_core.v` was 125,686 bytes with hash `6bedf9...`; `diff -q` reported files differ. | Provenance mismatch flagged |
| FPGA/ASIC synthesis | README includes example next steps, but packet did not run synthesis, P&R, timing, or formal checks. | Synthesis signoff blocked |