{ "packet_id": "ARK_AXIOM_WARPCORE_PUBLIC_RTL_REVIEW_PACKET_v0_1", "packet_type": "ark_axiom_rtl_review_compression_packet", "created_at": "2026-06-26", "review_mode": "bounded_public_demo_review_packet", "source_artifact": { "name": "WarpCore-main", "source_path": "/Users/zolboon/Downloads/WarpCore-main", "repo_url": "unavailable_in_local_snapshot", "commit_hash": "unavailable_no_git_metadata_in_downloaded_folder", "license_observed": "MIT-licensed per user-provided scope; not independently revalidated in this packet" }, "scope": { "included": [ "public local source snapshot", "Amaranth HDL source review-compression", "generated Verilog provenance review", "C++ simulator architecture comparison", "available simulator test execution", "ranked senior-review targets", "blocked claims and human-review questions" ], "excluded": [ "formal verification", "HDL tests beyond the shipped Amaranth testbench programs", "FPGA synthesis", "ASIC synthesis", "timing closure", "physical design review", "security review", "claim of GPU correctness" ] }, "packet_authorizes_execution": false, "human_operator_handoff": true, "verdict": { "status": "REVIEW_PACKET_ONLY", "summary": "Ark Axiom generated a bounded review-compression packet for a public Amaranth HDL GPU core. The shipped C++ simulator tests passed locally, the shipped Amaranth HDL testbench passed locally, and Verilog generation succeeded in a packet-local virtualenv. The packet still does not verify WarpCore, certify correctness, or approve FPGA/ASIC readiness." }, "architecture_summary": { "declared_hdl_core": { "warps": 2, "lanes_per_warp": 8, "threads": 16, "register_file": "2 warps x 8 lanes x 32 registers x 32 bits", "instruction_memory": "256 x 32-bit words in generation script", "data_memory": "1024 x 32-bit words / 4KB in generation script", "memory_latency": "4 cycles", "isa": "custom 32-bit fixed-width encoding" }, "declared_cpp_simulator": { "warps": 2, "lanes_per_warp": 8, "threads": 16, "memory": "64KB byte-addressed memory", "memory_latency": "4 cycles", "isa": "custom RISC-V-like Instruction object model" } }, "review_surface_compression": { "files_total": 43, "python_lines": 2622, "generated_verilog_lines": 4516, "cpp_and_header_lines": 1205, "compressed_to_ranked_targets": 12 }, "top_review_targets": [ { "rank": 1, "target": "HDL scheduler state-transition ordering", "why_it_matters": "Stall, halt, stall-counter decrement, readiness, and current-warp switching are concurrent sync/comb interactions. A senior reviewer should inspect whether same-cycle stall/halt requests and ready transitions behave as intended.", "evidence": [ "gpu-core/rtl/scheduler.py:66-99", "gpu-core/rtl/gpu_core.py:197-211", "gpu-core/rtl/gpu_core.py:343-355" ], "status": "HUMAN_REVIEW_RECOMMENDED" }, { "rank": 2, "target": "HDL SIMT lane execution versus eight-ALU claim", "why_it_matters": "The top-level core instantiates eight ALUs but drives only alus[0] while iterating current_lane. This may be an intentional area-saving simplification, but it conflicts with public wording around eight parallel lanes unless explicitly documented.", "evidence": [ "gpu-core/rtl/gpu_core.py:79-84", "gpu-core/rtl/gpu_core.py:243-357", "gpu-core/README.md:18-21", "gpu-core/README.md:52-54" ], "status": "CLAIM_REVIEW_REQUIRED" }, { "rank": 3, "target": "Simulator versus HDL ISA parity", "why_it_matters": "The HDL uses a 4-bit opcode fixed-width encoding while the simulator uses a richer enum/object ISA with additional operations and different opcode values. The simulator tests cannot be treated as direct HDL ISA conformance evidence without an explicit mapping table.", "evidence": [ "gpu-core/rtl/isa.py:17-43", "gpu-sim/include/isa.h:10-48", "README.md specs table reviewed during packet creation" ], "status": "PARITY_REVIEW_REQUIRED" }, { "rank": 4, "target": "Memory model parity and address-range assumptions", "why_it_matters": "HDL generation uses 4KB data memory and word-addressed conversion from byte addresses. The simulator uses 64KB byte-addressed memory and demo addresses such as 0x1000, 0x1100, and 0x2000 that exceed the 4KB HDL data-memory range if carried over directly.", "evidence": [ "gpu-core/build/generate_verilog.py:24", "gpu-core/rtl/gpu_core.py:313-319", "gpu-core/rtl/gpu_core.py:333-340", "gpu-sim/include/config.h:14", "gpu-sim/src/main.cpp:32-39", "gpu-sim/src/main.cpp:86-101" ], "status": "BOUNDARY_REVIEW_REQUIRED" }, { "rank": 5, "target": "LOAD/STORE latency semantics", "why_it_matters": "HDL performs memory read/write in the lane iteration flow and then stalls the warp after all lanes complete. A reviewer should confirm whether the modeled latency is architectural, cosmetic, or sufficient for the intended memory implementation.", "evidence": [ "gpu-core/rtl/gpu_core.py:313-319", "gpu-core/rtl/gpu_core.py:333-355", "gpu-core/rtl/scheduler.py:77-82" ], "status": "LATENCY_MODEL_REVIEW_REQUIRED" }, { "rank": 6, "target": "HALT behavior and all-halted detection", "why_it_matters": "HALT is signaled to the scheduler from the EXECUTE state. A reviewer should inspect whether halt requests are captured correctly across sync timing and whether done behavior can miss or delay finishing conditions.", "evidence": [ "gpu-core/rtl/gpu_core.py:245-251", "gpu-core/rtl/scheduler.py:73-75", "gpu-core/rtl/scheduler.py:96-99" ], "status": "HUMAN_REVIEW_RECOMMENDED" }, { "rank": 7, "target": "Register-file integration and address encoding", "why_it_matters": "There is a standalone RegisterFile module and an inline Memory-based register file inside the top-level core. Both use warp/lane/register address concepts. A reviewer should confirm the standalone module is not stale or inconsistent with integrated behavior.", "evidence": [ "gpu-core/rtl/regfile.py:11-72", "gpu-core/rtl/gpu_core.py:102-108", "gpu-core/rtl/gpu_core.py:284-286", "gpu-core/rtl/gpu_core.py:324-330" ], "status": "PROVENANCE_REVIEW_REQUIRED" }, { "rank": 8, "target": "Lane masking and active-thread assumptions", "why_it_matters": "The simulator has active_mask support, but the HDL path reviewed here assumes all lanes through current_lane iteration and does not expose divergence or mask control in the top-level path.", "evidence": [ "gpu-sim/include/warp.h:20-32", "gpu-sim/include/gpu_core.h:178-183", "gpu-core/rtl/gpu_core.py:243-357" ], "status": "FEATURE_PARITY_REVIEW_REQUIRED" }, { "rank": 9, "target": "Branch semantics and lane-0 decision model", "why_it_matters": "Both HDL and simulator appear to use lane 0 for branch decisions. This should be documented as a SIMT control-flow assumption and tested across taken/not-taken, negative offsets, and per-lane divergence cases.", "evidence": [ "gpu-core/rtl/gpu_core.py:253-280", "gpu-sim/include/gpu_core.h:151-165", "gpu-sim/src/main.cpp:115-150" ], "status": "CONTROL_FLOW_REVIEW_REQUIRED" }, { "rank": 10, "target": "Generated Verilog provenance", "why_it_matters": "Generated Verilog exists in the snapshot and was successfully regenerated in the packet-local environment, but regenerated Verilog differs from the downloaded checked-in generated file. A reviewer should pin toolchain versions and compare semantic differences before making provenance claims.", "evidence": [ "gpu-core/build/generate_verilog.py:20-55", "gpu-core/build/gpu_core.v downloaded hash recorded in artifact manifest", "run_receipt.md regenerated Verilog hash recorded" ], "status": "REGENERATION_EXECUTED_DIFF_REVIEW_REQUIRED" }, { "rank": 11, "target": "Test coverage claims versus executed evidence", "why_it_matters": "The C++ simulator tests passed locally and the shipped HDL testbench passed locally. This is useful execution evidence for shipped demos, but it is still bounded smoke/integration coverage rather than formal proof, synthesis signoff, or simulator/HDL equivalence.", "evidence": [ "gpu-sim/tests/test_gpu.cpp:236-266", "gpu-core/tb/test_gpu.py:354-364", "run_receipt.md" ], "status": "SHIPPED_TESTS_PASSED_SCOPE_BOUNDED" }, { "rank": 12, "target": "Synthesis-script assumptions", "why_it_matters": "README gives FPGA and ASIC next-step commands/targets, but this packet did not run Yosys, nextpnr, OpenROAD, timing, area, or P&R checks.", "evidence": [ "gpu-core/README.md:139-152", "gpu-core/build/generate_verilog.py:125-128" ], "status": "SYNTHESIS_SIGNOFF_BLOCKED" } ], "blocked_claims": [ "WARPCORE_VERIFIED", "GPU_CORRECTNESS_PROVEN", "FORMAL_PROOF_COMPLETE", "FPGA_READY", "ASIC_READY", "SYNTHESIS_SIGNOFF_COMPLETE", "TIMING_CLOSURE_CONFIRMED", "SECURITY_SAFE", "SIMULATOR_HDL_EQUIVALENCE_PROVEN", "EXHAUSTIVE_TESTS_PASSED", "PRODUCTION_READY", "ARK_AXIOM_FOUND_BUGS" ], "allowed_claims": [ "ARK_AXIOM_GENERATED_BOUNDED_RTL_REVIEW_COMPRESSION_PACKET", "RANKED_REVIEW_TARGETS_IDENTIFIED", "SIMULATOR_TESTS_EXECUTED_LOCALLY", "SHIPPED_HDL_TESTBENCH_EXECUTED_LOCALLY", "VERILOG_REGENERATION_EXECUTED_LOCALLY", "REGENERATED_VERILOG_DIFFERS_FROM_DOWNLOADED_GENERATED_VERILOG", "HUMAN_HARDWARE_REVIEW_RECOMMENDED", "PACKET_AUTHORIZES_EXECUTION_FALSE" ], "human_review_required": true }