# Run Receipt

Packet: `ARK_AXIOM_WARPCORE_PUBLIC_RTL_REVIEW_PACKET_v0_1`

Date: 2026-06-26

Mode: bounded public-demo RTL review-compression packet

Source:

- `/Users/zolboon/Downloads/WarpCore-main`
- Git commit: unavailable, local folder has no `.git` metadata

Scratch run directory:

- `/private/tmp/ark_axiom_warpcore_review/WarpCore-main`

Executed checks:

| Check | Command | Result |
|---|---|---|
| C++ simulator test suite | `make test` in `gpu-sim` scratch copy | Passed: 14 passed, 0 failed |
| Packet-local Python environment | `python3 -m venv artifacts/ARK_AXIOM_WARPCORE_PUBLIC_RTL_REVIEW_PACKET_v0_1/.venv` | Created |
| HDL dependencies | `.venv/bin/python -m pip install amaranth amaranth-yosys` | Installed `amaranth==0.5.8`, `amaranth-yosys==0.50.0.0.post124` |
| HDL testbench | `.venv/bin/python tb/test_gpu.py` in `gpu-core` scratch copy | Passed shipped simple ALU, vector add, and scalar multiply programs |
| Verilog generation | `.venv/bin/python build/generate_verilog.py` in `gpu-core` scratch copy | Passed; generated `alu.v`, `decoder.v`, `scheduler.v`, `gpu_core.v` |
| Downloaded/generated Verilog comparison | `diff -q downloaded gpu_core.v regenerated gpu_core.v` | Files differ |

HDL testbench summary:

- Simple ALU: completed in 14 cycles.
- Vector addition: completed in 38 cycles, 7 warp switches, all 8 outputs matched expected values.
- Scalar multiply: completed in 34 cycles, 5 warp switches, all 16 thread outputs matched expected values.

Regenerated Verilog hashes:

```text
dc210194689bafb5f268048246481c3c5762af284c1af838ca70cbcc1b910c52  build/alu.v
9e79c3cf451ce0f7df8caa353b3f313b05fdda06f8fc591b854c21e8461c688b  build/decoder.v
60bdd08d629dc63bce33f20464dbb1477a4e18060b910dd1061549bbc8c0cad8  build/scheduler.v
6bedf9bb69c96b9473962dfacdbb1ec58b531bb7bd2cfedfb935a3d6c7b3844c  build/gpu_core.v
```

Downloaded versus regenerated `gpu_core.v`:

```text
115355 bytes  /Users/zolboon/Downloads/WarpCore-main/gpu-core/build/gpu_core.v
125686 bytes  /private/tmp/ark_axiom_warpcore_review/WarpCore-main/gpu-core/build/gpu_core.v
```

Execution authorization:

```json
{
  "packet_authorizes_execution": false,
  "human_operator_handoff": true,
  "blocked_execution_claims": [
    "WARPCORE_VERIFIED",
    "GPU_CORRECTNESS_PROVEN",
    "FPGA_READY",
    "ASIC_READY",
    "SYNTHESIS_SIGNOFF_COMPLETE"
  ]
}
```

Run conclusion:

The simulator evidence and shipped HDL testbench evidence are useful, but they are not formal proof, exhaustive verification, synthesis signoff, or simulator/HDL equivalence evidence. Verilog regeneration succeeded, but regenerated Verilog differs from the downloaded generated Verilog artifact, so generated-RTL provenance remains a review target.