Ark Axiom compresses the review surface where generated hardware, board evidence, and the software stack meet human engineering judgment. The packet shows what should be reviewed first, what evidence exists, and which claims remain blocked.
Fixed scope. Three business day standard evaluation. No ranked review packet produced → no fee. Review-prioritization metrics are not correctness, coverage, readiness, or signoff claims. Every Ark Axiom review agent runs behind an Evaluation Gate: it can rank review targets and preserve evidence, but it cannot approve signoff, fabrication, tapeout, benchmark validity, or production readiness.
Ark Axiom compresses the review surface where generated hardware, board evidence, and the software stack meet human engineering judgment.
Compresses RTL review surfaces before formal verification, DV, or manual review begins. It ranks signals, cones, FSM drift, and candidate assertion questions for engineer inspection.
Compresses board, BOM, fab-package, and firmware-to-board assumptions into ranked review blockers. Gate means claim/action boundary, not manufacturing approval.
Fixture-backed v0.1 lane for compiler output, ISA assumptions, simulator behavior, runtime assumptions, benchmark claims, and RTL evidence. Early lane means normalized evidence packet, not compiler verification.
A review agent that overclaims is a liability. Ark Axiom blocks correctness, signoff, manufacturing, benchmark, and replacement claims. The packet is a bounded review queue, not permission to tape out, fabricate, ship, or trust a benchmark.
packet_authorizes_execution:falsehuman_operator_handoff:trueBefore Ark Axiom reviews RTL, PCB, BOM, firmware, fab-package, or compiler-hardware evidence, the evaluation scope is converted into a bounded authority envelope.
Axiom Evaluation Gate controls what a review agent may read, derive, claim, export, and hand off during a bounded hardware evaluation. The gate defines what artifacts may be inspected, what evidence may be derived, what claims are blocked, what outputs may be exported, what must be handed to a human engineer, and what remains outside scope.
The review agent may rank, localize, summarize, and preserve evidence. It may not approve signoff, fabrication, tapeout, benchmark validity, compiler correctness, RTL correctness, BOM correctness, DRC/ERC, SI/PI, safety, or production readiness.
{
"axiom_evaluation_gate": {
"gate_id": "AXIOM_EVAL_GATE_v0_1",
"review_mode": "rtl_review | pcb_eco | fab_readiness | firmware_hardware | compiler_hardware",
"scope_envelope": {
"artifact_types_allowed": ["rtl", "pcb", "bom", "firmware_config", "compiler_evidence"],
"source_access": "sanitized | nda | public_fixture",
"production_access_allowed": false,
"credential_access_allowed": false,
"external_side_effect_allowed": false
},
"allowed_agent_actions": [
"rank_review_targets",
"localize_evidence",
"summarize_drift",
"emit_reason_codes",
"hash_artifacts",
"produce_review_packet"
],
"blocked_agent_actions": [
"approve_signoff",
"approve_fabrication",
"approve_tapeout",
"approve_benchmark",
"modify_source_artifacts",
"submit_to_fab",
"replace_engineer_review"
],
"human_operator_handoff": true,
"packet_authorizes_execution": false,
"zero_signoff_authority": true
}
}
These boundaries are not disclaimers. They are the architecture. A review agent that overclaims is a liability, not a tool.
Controlled ECOs and historical replay cases on public boards and public RTL. Customer artifacts evaluated only under NDA. View the packet mode map → · Open evidence graph →
Scoped proof artifacts and technical demos. Not production signoff claims.
| Evidence Track | Best Current Proof | What It Supports | What It Does Not Claim |
|---|---|---|---|
| RTL Review Compression | 15 / 15 public replay cases | Ranked review-target and signal localization for bounded public RTL repair contexts | Bug detection, formal proof, RTL correctness, DV signoff |
| RTL Assertion Gate | 5 cases · 2 strong · 3 partial | Candidate SVA, assumptions, vacuity warnings, human approval questions | Final specs, proof success, non-vacuous proof, DV engineering replacement |
| PCB ECO Gate | System76 Launch public KiCad history | Board-revision review blockers for routing, power, ground, debug, boot/control | DRC/ERC, SI/PI, thermal validation, manufacturing readiness |
| BOM / AVL-Style Evidence | nSealr TROPIC01 public BOM path | BOM/AVL-style review evidence in controlled and real before/after BOM path | BOM correctness, AVL approval, substitute-part suitability, DFM |
| PCB Fab Readiness Gate | Complete + missing fixture packages | Checks for expected source, Gerber, drill, BOM, CPL/PNP, stackup, DRC/ERC presence | File correctness, manufacturability, electrical behavior, certification |
| Firmware-Hardware Gate | 7 deterministic fixtures | Review blockers for MCU identity, pin assumptions, UART/I2C/SPI drift, boot conflicts | Firmware correctness, HIL testing, board bring-up, safety certification |
| Compiler-Hardware Assumption Gate v0.1 | Fixture-backed packet · 16 targets · SHA-256 verified | Assumption review across ISA, simulator, runtime, benchmark, memory, and RTL evidence | Compiler correctness, simulator/RTL equivalence, benchmark validation, performance portability, hardware readiness |
A fixed-scope engagement, not a software deployment. Runs alongside your existing review workflows without replacing EDA, DRC/ERC, or signoff.
Hardware teams that need review compression before signoff — not autonomous AI making engineering decisions.
One bounded RTL, PCB/BOM, fab-readiness, firmware-hardware, or early compiler-hardware assumption review packet. Scope and NDA agreed before intake.