Three review surfaces. One packet discipline.

Ark Axiom compresses the review surface where generated hardware, board evidence, and the software stack meet human engineering judgment.

Homepage rule: keep the public product surface to RTL Review Agent, PCB Review Gate, and the early Compiler-Hardware Assumption Gate lane. PCB sub-gates remain packet modes under PCB Review Gate, not separate homepage products.

Current

RTL Review Agent

Compresses RTL review surfaces before formal verification, DV, or manual review begins.

Signal, cone, FSM, clock, and reset-domain review targets.

Public replay and generated-HDL packet examples.

Does not claim RTL correctness, bug detection, or DV signoff.

Current

PCB Review Gate

Umbrella gate for PCB revision, ECO, fab-readiness, and firmware-to-board assumption packet modes.

Board/BOM revision witness and ECO blockers.

Fab package completeness and firmware-hardware assumptions.

Gate means claim/action boundary, not manufacturing approval.

Early Lane

Compiler-Hardware Assumption Gate

Fixture-backed v0.1 lane for compiler output, ISA assumptions, simulator behavior, runtime assumptions, benchmark claims, and RTL evidence.

16-target public demo packet: 8 P1 and 8 P2.

Normalized evidence inputs now; importers later.

Does not prove compiler correctness or simulator/RTL equivalence.

PCB Review Gate Packet Modes

Mode	Status	Purpose	Blocked Claims
PCB Tamper Witness / Revision Witness	Executable	Detects board and BOM revision drift: nets, components, traces, vias, text, BOM substitutions, movement, and routing changes.	Malicious intent, board correctness, production failure, inspection replacement.
PCB ECO Gate	Executable	Turns revision drift into ordered review blockers and evidence requests before fab or assembly.	Severity, signoff, manufacturability, DRC/ERC, SI/PI, engineering approval.
PCB Fab Readiness Gate	Executable	Checks whether a fab/assembly package is complete enough to review: source, Gerbers, drills, BOM, CPL/PNP, stackup, DRC/ERC reports, and fab drawing.	File correctness, manufacturability, electrical behavior, certification, production signoff.
Firmware-Hardware Assumption Gate	Executable	Checks firmware-to-board assumptions: MCU identity, GPIO mappings, UART/I2C/SPI expectations, boot/reset/debug pins, build/flash/log evidence.	Firmware correctness, HIL readiness, board bring-up, production release, human firmware/EE review replacement.

Future Axiom Lanes

Lane	Status	Evidence Needed Before Public Core	Claim Boundary
Analog Circuit Review Gate	Future	SPICE/netlist inputs, operating points, AC/transient evidence, stability/tolerance review targets.	No analog correctness, stability proof, THD proof, manufacturability, or human analog-review replacement.
Generated Analog Topology Review Gate	Future	Generated circuit topology graphs, feedback-path evidence, simulation objective boundaries, designer review questions.	A simulated topology is not a trustworthy circuit or production-ready design.
Mixed-Signal Assumption Gate	Future	Digital/analog interface assumptions, clock/reset/reference domains, ADC/DAC evidence, simulation and board context.	No mixed-signal correctness, silicon readiness, safety certification, or signoff.

Sample Packet Links

RTL

Public RTL Packets

Historical replay and generated-HDL review packets.

Open RTL samples

PCB

Public PCB Packets

Public board ECO review samples and PCB ECO Gate evidence.

Open PCB samples

Early Lane

Compiler-Hardware Demo

Fixture-backed packet with blocked benchmark/equivalence claims and SHA-256 evidence.

Open Compiler-Hardware sample

Evidence Graph

Packets, Proofs, Hashes

One path across packet pages, raw JSON/CSV/MD artifacts, receipts, SHA manifests, and blocked-claim boundaries.

Open evidence graph