Ark Evaluation Packet
RTL Review Sample Packets - Public RTL v0.1
Generated: 2026-06-04T02:20:39.407941+00:00
Claim boundary: Public RTL sample packet. Review triage only; not formal verification, not simulation, not LEC, not security signoff, and not an upstream defect claim.
Buyer-safe framing: These examples show ranked review targets, affected local signal context, and reproducible handoff artifacts on public RTL. They are samples of review triage output, not verification closure.
Sample Cases
| Case | Title | Sample type | Source | Review compression | Signal-context isolation | Targets |
|---|---|---|---|---|---|---|
| 01_ibex_instruction_fetch_replay | Ibex Instruction-Fetch Control Replay | historical repair replay | Ibex | 2278.0x | 32.3077x | 1 |
| 02_cva6_mmu_replay | CVA6 MMU / TLB Context Replay | historical repair replay | CVA6 | 762.0x | 64.5x | 2 |
| 03_opentitan_spi_host_fsm_replay | OpenTitan SPI Host FSM Replay | historical repair replay | OpenTitan | 349.3333x | 10.0714x | 3 |
| 04_axi_priority_encoder_controlled | AXI Priority Encoder Output-Path Sample | controlled public RTL change | alexforencich/verilog-axi | 92.0x | 8.6667x | 1 |
| 05_picorv32_memory_handshake_controlled | PicoRV32 Memory Handshake Sample | controlled public RTL change | YosysHQ/picorv32 | 3049.0x | 49.7692x | 1 |
Links
- Ibex Instruction-Fetch Control Replay
- CVA6 MMU / TLB Context Replay
- OpenTitan SPI Host FSM Replay
- AXI Priority Encoder Output-Path Sample
- PicoRV32 Memory Handshake Sample