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      "required_evidence": [
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        "runtime trace",
        "fallback attribution",
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        "reproduction steps"
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      "title": "Benchmark claim requires review: PERFORMANCE_CLAIM_VALIDATED"
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        "review_question": "Which data_memory_bytes value is authoritative for compiler, simulator, RTL, and runtime evidence?",
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          "isa": 4096,
          "rtl": 4096,
          "simulator": 65536
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      "human_review_question": "Which data_memory_bytes value is authoritative for compiler, simulator, RTL, and runtime evidence?",
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          "observed_memory_bytes": 8192
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        "RTL execute source",
        "instruction-level RTL trace",
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      "title": "VDOT8 selected without RTL decode/execute support"
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      "detail": "instruction exists in compiler selection table but is absent from RTL decode/execute references",
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          "mnemonic": "VDOT8"
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      "required_evidence": [
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        "simulator trace comparison"
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    {
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      "detail": "Simulator-only evidence cannot establish simulator/RTL equivalence.",
      "evidence": {
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          "trace_required": true
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      "human_review_question": "What paired simulator and RTL traces support or refute this behavior?",
      "id": "sim_rtl_equivalence_boundary:claim_003",
      "permitted_claim": "SIMULATOR_RTL_REVIEW_TARGET",
      "required_evidence": [
        "paired simulator trace",
        "RTL trace",
        "instruction-by-instruction comparison",
        "known divergence list"
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      "title": "Simulator/RTL equivalence claim has no RTL trace evidence"
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    {
      "attention_priority": "P1",
      "category": "unsupported_op_fallback",
      "detail": "Generated hardware benchmark or end-to-end claim may include non-accelerator execution.",
      "evidence": {
        "fallback": {
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          "fallback": "HOST_FALLBACK",
          "op_id": "op_003",
          "reason": "no hardware RELU instruction in current ISA table",
          "source_op": "relu_i32"
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        "operation": {
          "assumption": "runtime will merge host fallback result into accelerator output buffer",
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          "selected_instruction": "HOST_FALLBACK",
          "source_op": "relu_i32"
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      "human_review_question": "Does the benchmark separate accelerator execution from host fallback work?",
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      "required_evidence": [
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        "runtime fallback log",
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        "accelerator-only timing evidence"
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    {
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      "category": "generated_artifact_provenance_gap",
      "detail": "Generated hardware artifact lacks generator version or source manifest evidence.",
      "evidence": {
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          "generator": "python-hdl-demo",
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          "source_manifest": null
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      "permitted_claim": "REVIEW_TARGET",
      "required_evidence": [
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        "source manifest",
        "generated RTL hash",
        "reproduction command"
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      "title": "Generated RTL provenance is incomplete"
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      "evidence": {
        "operation": {
          "assumption": "store commits before HALT is observed by host",
          "evidence": "not covered by generated trace",
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          "source_op": "store_i8x8"
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      "human_review_question": "Is the store/retire/HALT ordering evidenced in both simulator and RTL behavior?",
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        "runtime completion contract"
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      "evidence": {
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          "rtl": 8,
          "simulator": 1
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      "human_review_question": "Which alignment_bytes value is authoritative for compiler, simulator, RTL, and runtime evidence?",
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      "category": "memory_layout_mismatch",
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          "simulator": 2
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      "human_review_question": "Which load_latency_cycles value is authoritative for compiler, simulator, RTL, and runtime evidence?",
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      "detail": "Compiler, simulator, RTL, ISA, or runtime evidence disagree on a memory assumption.",
      "evidence": {
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        "review_question": "Which store_latency_cycles value is authoritative for compiler, simulator, RTL, and runtime evidence?",
        "values": {
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          "rtl": 2,
          "simulator": 2
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      "human_review_question": "Which store_latency_cycles value is authoritative for compiler, simulator, RTL, and runtime evidence?",
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      "permitted_claim": "MEMORY_LAYOUT_REVIEW_TARGET",
      "required_evidence": [
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        "compiler lowering metadata",
        "simulator config",
        "RTL memory map",
        "runtime driver contract"
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      "title": "Memory model mismatch: store_latency_cycles"
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    {
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      "category": "simulator_rtl_behavior_mismatch",
      "detail": "store-retirement ordering before HALT is not evidenced in RTL trace",
      "evidence": {
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          "mnemonic": "HALT"
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      "human_review_question": "What RTL trace or source reference closes this compiler-hardware assumption?",
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      "required_evidence": [
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        "fallback attribution log",
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      "evidence": {
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          "public_reproduction_steps": false,
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          "unit_tests": [
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      "human_review_question": "Which behavior is actually covered by unit, simulator, RTL, and public reproduction evidence?",
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      "permitted_claim": "REVIEW_TARGET",
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        "simulator tests",
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        "negative tests",
        "public reproduction steps"
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    }
  ],
  "schema": "ARK_COMPILER_HARDWARE_ASSUMPTION_GATE_v0.1",
  "service": "ark_compiler_hardware_assumption_gate",
  "simulator_rtl_questions": [
    {
      "question": "Can RTL decode and execute this instruction with the same semantics assumed by the compiler?",
      "required_evidence": [
        "RTL decode source",
        "RTL execute source",
        "instruction-level RTL trace",
        "compiler instruction-selection rule"
      ],
      "target_id": "rtl_absent:op_002:VDOT8",
      "title": "VDOT8 selected without RTL decode/execute support"
    },
    {
      "question": "What RTL trace or source reference closes this compiler-hardware assumption?",
      "required_evidence": [
        "RTL source reference",
        "decode/execute trace",
        "simulator trace comparison"
      ],
      "target_id": "rtl_known_gap:VDOT8",
      "title": "Known RTL evidence gap for VDOT8"
    },
    {
      "question": "What paired simulator and RTL traces support or refute this behavior?",
      "required_evidence": [
        "paired simulator trace",
        "RTL trace",
        "instruction-by-instruction comparison",
        "known divergence list"
      ],
      "target_id": "sim_rtl_equivalence_boundary:claim_003",
      "title": "Simulator/RTL equivalence claim has no RTL trace evidence"
    },
    {
      "question": "What RTL trace or source reference closes this compiler-hardware assumption?",
      "required_evidence": [
        "RTL source reference",
        "decode/execute trace",
        "simulator trace comparison"
      ],
      "target_id": "rtl_known_gap:HALT",
      "title": "Known RTL evidence gap for HALT"
    }
  ],
  "target_count": 16,
  "unsupported_fallbacks": [
    {
      "benchmark_visible": true,
      "fallback": "HOST_FALLBACK",
      "op_id": "op_003",
      "reason": "no hardware RELU instruction in current ISA table",
      "source_op": "relu_i32"
    }
  ],
  "verdict": "HUMAN_REVIEW_REQUIRED"
}