[
  {
    "attention_priority": "P1",
    "category": "benchmark_claim_unsupported_by_trace",
    "detail": "Benchmark or end-to-end acceleration claim is not supported by enough accelerator-only trace evidence.",
    "evidence": {
      "claim": {
        "claim_type": "END_TO_END_ACCELERATION_PROVEN",
        "id": "claim_001",
        "supporting_evidence": [
          "simulator_trace_summary.json"
        ],
        "text": "The generated kernel runs end-to-end on the accelerator.",
        "trace_required": true
      },
      "trace_count": 1,
      "unsupported_fallbacks": [
        {
          "benchmark_visible": true,
          "fallback": "HOST_FALLBACK",
          "op": "relu_i32",
          "reason": "unsupported op in hardware target"
        }
      ]
    },
    "human_review_question": "Which traces separate accelerator execution, host fallback, runtime overhead, and repeated benchmark evidence?",
    "id": "benchmark_boundary:claim_001",
    "permitted_claim": "BENCHMARK_CLAIM_BOUNDARY",
    "required_evidence": [
      "accelerator-only trace",
      "runtime trace",
      "fallback attribution",
      "benchmark repetitions",
      "reproduction steps"
    ],
    "title": "Benchmark claim requires review: END_TO_END_ACCELERATION_PROVEN"
  },
  {
    "attention_priority": "P1",
    "category": "benchmark_claim_unsupported_by_trace",
    "detail": "Benchmark or end-to-end acceleration claim is not supported by enough accelerator-only trace evidence.",
    "evidence": {
      "claim": {
        "claim_type": "PERFORMANCE_CLAIM_VALIDATED",
        "id": "claim_002",
        "supporting_evidence": [
          "single simulator smoke trace"
        ],
        "text": "The compiler target validates ARK_DEMO_VEC8 performance for vector dot workloads.",
        "trace_required": true
      },
      "trace_count": 1,
      "unsupported_fallbacks": [
        {
          "benchmark_visible": true,
          "fallback": "HOST_FALLBACK",
          "op": "relu_i32",
          "reason": "unsupported op in hardware target"
        }
      ]
    },
    "human_review_question": "Which traces separate accelerator execution, host fallback, runtime overhead, and repeated benchmark evidence?",
    "id": "benchmark_boundary:claim_002",
    "permitted_claim": "BENCHMARK_CLAIM_BOUNDARY",
    "required_evidence": [
      "accelerator-only trace",
      "runtime trace",
      "fallback attribution",
      "benchmark repetitions",
      "reproduction steps"
    ],
    "title": "Benchmark claim requires review: PERFORMANCE_CLAIM_VALIDATED"
  },
  {
    "attention_priority": "P1",
    "category": "memory_layout_mismatch",
    "detail": "Compiler, simulator, RTL, ISA, or runtime evidence disagree on a memory assumption.",
    "evidence": {
      "assumption": "data_memory_bytes",
      "review_question": "Which data_memory_bytes value is authoritative for compiler, simulator, RTL, and runtime evidence?",
      "values": {
        "compiler": 8192,
        "isa": 4096,
        "rtl": 4096,
        "simulator": 65536
      }
    },
    "human_review_question": "Which data_memory_bytes value is authoritative for compiler, simulator, RTL, and runtime evidence?",
    "id": "memory_mismatch:data_memory_bytes",
    "permitted_claim": "MEMORY_LAYOUT_REVIEW_TARGET",
    "required_evidence": [
      "ISA memory model",
      "compiler lowering metadata",
      "simulator config",
      "RTL memory map",
      "runtime driver contract"
    ],
    "title": "Memory model mismatch: data_memory_bytes"
  },
  {
    "attention_priority": "P1",
    "category": "memory_layout_mismatch",
    "detail": "The trace is not bounded by the supplied RTL data-memory size.",
    "evidence": {
      "rtl_data_memory_bytes": 4096,
      "trace": {
        "halt_after_store_observed": false,
        "instructions_executed": [
          "VLOAD",
          "VLOAD",
          "VDOT8",
          "HOST_FALLBACK",
          "VSTORE",
          "HALT"
        ],
        "kernel": "int8_vector_dot_then_store",
        "notes": "Simulator permits 64KB memory and records host fallback as a successful op.",
        "observed_latency_cycles": 14,
        "observed_memory_bytes": 8192
      }
    },
    "human_review_question": "Would this kernel fit in the RTL memory map without simulator-only capacity?",
    "id": "memory_trace_exceeds_rtl:int8_vector_dot_then_store",
    "permitted_claim": "MEMORY_LAYOUT_REVIEW_TARGET",
    "required_evidence": [
      "simulator trace",
      "RTL memory map",
      "linker/runtime allocation map"
    ],
    "title": "Simulator trace uses more memory than RTL model"
  },
  {
    "attention_priority": "P1",
    "category": "simulator_rtl_behavior_mismatch",
    "detail": "Compiler or ISA evidence references an instruction that is absent from supplied RTL decode/execute references.",
    "evidence": {
      "isa_entry": {
        "latency_cycles": 4,
        "mnemonic": "VDOT8",
        "opcode": "0x30",
        "operands": [
          "acc",
          "va",
          "vb"
        ],
        "semantics": "acc += sum(va[i] * vb[i]) for i in 0..7",
        "supported_by_rtl": false
      },
      "operation": {
        "assumption": "hardware supports VDOT8 with int32 accumulator",
        "evidence": "selected by vec8 pattern rule dot_i8x8",
        "id": "op_002",
        "selected_instruction": "VDOT8",
        "source_op": "dot_i8x8_i32"
      },
      "rtl_mnemonics": [
        "HALT",
        "VADD8",
        "VLOAD",
        "VMUL8",
        "VSTORE"
      ]
    },
    "human_review_question": "Can RTL decode and execute this instruction with the same semantics assumed by the compiler?",
    "id": "rtl_absent:op_002:VDOT8",
    "permitted_claim": "SIMULATOR_RTL_REVIEW_TARGET",
    "required_evidence": [
      "RTL decode source",
      "RTL execute source",
      "instruction-level RTL trace",
      "compiler instruction-selection rule"
    ],
    "title": "VDOT8 selected without RTL decode/execute support"
  },
  {
    "attention_priority": "P1",
    "category": "simulator_rtl_behavior_mismatch",
    "detail": "instruction exists in compiler selection table but is absent from RTL decode/execute references",
    "evidence": {
      "gap": {
        "gap": "instruction exists in compiler selection table but is absent from RTL decode/execute references",
        "mnemonic": "VDOT8"
      }
    },
    "human_review_question": "What RTL trace or source reference closes this compiler-hardware assumption?",
    "id": "rtl_known_gap:VDOT8",
    "permitted_claim": "SIMULATOR_RTL_REVIEW_TARGET",
    "required_evidence": [
      "RTL source reference",
      "decode/execute trace",
      "simulator trace comparison"
    ],
    "title": "Known RTL evidence gap for VDOT8"
  },
  {
    "attention_priority": "P1",
    "category": "simulator_rtl_behavior_mismatch",
    "detail": "Simulator-only evidence cannot establish simulator/RTL equivalence.",
    "evidence": {
      "claim": {
        "claim_type": "SIMULATOR_RTL_EQUIVALENCE_PROVEN",
        "id": "claim_003",
        "supporting_evidence": [],
        "text": "Simulator and RTL behavior are equivalent for the demo kernel.",
        "trace_required": true
      },
      "rtl_trace_count": 0
    },
    "human_review_question": "What paired simulator and RTL traces support or refute this behavior?",
    "id": "sim_rtl_equivalence_boundary:claim_003",
    "permitted_claim": "SIMULATOR_RTL_REVIEW_TARGET",
    "required_evidence": [
      "paired simulator trace",
      "RTL trace",
      "instruction-by-instruction comparison",
      "known divergence list"
    ],
    "title": "Simulator/RTL equivalence claim has no RTL trace evidence"
  },
  {
    "attention_priority": "P1",
    "category": "unsupported_op_fallback",
    "detail": "Generated hardware benchmark or end-to-end claim may include non-accelerator execution.",
    "evidence": {
      "fallback": {
        "benchmark_visible": true,
        "fallback": "HOST_FALLBACK",
        "op_id": "op_003",
        "reason": "no hardware RELU instruction in current ISA table",
        "source_op": "relu_i32"
      },
      "operation": {
        "assumption": "runtime will merge host fallback result into accelerator output buffer",
        "fallback_reason": "no hardware RELU instruction in current ISA table",
        "id": "op_003",
        "selected_instruction": "HOST_FALLBACK",
        "source_op": "relu_i32"
      }
    },
    "human_review_question": "Does the benchmark separate accelerator execution from host fallback work?",
    "id": "unsupported_fallback:op_003",
    "permitted_claim": "UNSUPPORTED_FALLBACK_REVIEW_TARGET",
    "required_evidence": [
      "lowering trace",
      "runtime fallback log",
      "benchmark attribution by op",
      "accelerator-only timing evidence"
    ],
    "title": "relu_i32 lowered to host fallback"
  },
  {
    "attention_priority": "P2",
    "category": "generated_artifact_provenance_gap",
    "detail": "Generated hardware artifact lacks generator version or source manifest evidence.",
    "evidence": {
      "generated_rtl": {
        "generated": true,
        "generator": "python-hdl-demo",
        "generator_version": null,
        "source_manifest": null
      }
    },
    "human_review_question": "Can the generated RTL be traced back to the generator version, source inputs, and manifest used for this packet?",
    "id": "generated_artifact_provenance:rtl",
    "permitted_claim": "REVIEW_TARGET",
    "required_evidence": [
      "generator version",
      "source manifest",
      "generated RTL hash",
      "reproduction command"
    ],
    "title": "Generated RTL provenance is incomplete"
  },
  {
    "attention_priority": "P2",
    "category": "lowering_path_drift",
    "detail": "The lowering path depends on execution ordering that should be checked against simulator and RTL traces.",
    "evidence": {
      "operation": {
        "assumption": "store commits before HALT is observed by host",
        "evidence": "not covered by generated trace",
        "id": "op_004",
        "selected_instruction": "VSTORE",
        "source_op": "store_i8x8"
      }
    },
    "human_review_question": "Is the store/retire/HALT ordering evidenced in both simulator and RTL behavior?",
    "id": "lowering_order:op_004",
    "permitted_claim": "LOWERING_PATH_REVIEW_TARGET",
    "required_evidence": [
      "simulator trace",
      "RTL trace",
      "pipeline retire documentation",
      "runtime completion contract"
    ],
    "title": "store_i8x8 depends on ordering assumption"
  },
  {
    "attention_priority": "P2",
    "category": "memory_layout_mismatch",
    "detail": "Compiler, simulator, RTL, ISA, or runtime evidence disagree on a memory assumption.",
    "evidence": {
      "assumption": "alignment_bytes",
      "review_question": "Which alignment_bytes value is authoritative for compiler, simulator, RTL, and runtime evidence?",
      "values": {
        "compiler": 8,
        "rtl": 8,
        "simulator": 1
      }
    },
    "human_review_question": "Which alignment_bytes value is authoritative for compiler, simulator, RTL, and runtime evidence?",
    "id": "memory_mismatch:alignment_bytes",
    "permitted_claim": "MEMORY_LAYOUT_REVIEW_TARGET",
    "required_evidence": [
      "ISA memory model",
      "compiler lowering metadata",
      "simulator config",
      "RTL memory map",
      "runtime driver contract"
    ],
    "title": "Memory model mismatch: alignment_bytes"
  },
  {
    "attention_priority": "P2",
    "category": "memory_layout_mismatch",
    "detail": "Compiler, simulator, RTL, ISA, or runtime evidence disagree on a memory assumption.",
    "evidence": {
      "assumption": "load_latency_cycles",
      "review_question": "Which load_latency_cycles value is authoritative for compiler, simulator, RTL, and runtime evidence?",
      "values": {
        "compiler": 1,
        "rtl": 2,
        "simulator": 2
      }
    },
    "human_review_question": "Which load_latency_cycles value is authoritative for compiler, simulator, RTL, and runtime evidence?",
    "id": "memory_mismatch:load_latency_cycles",
    "permitted_claim": "MEMORY_LAYOUT_REVIEW_TARGET",
    "required_evidence": [
      "ISA memory model",
      "compiler lowering metadata",
      "simulator config",
      "RTL memory map",
      "runtime driver contract"
    ],
    "title": "Memory model mismatch: load_latency_cycles"
  },
  {
    "attention_priority": "P2",
    "category": "memory_layout_mismatch",
    "detail": "Compiler, simulator, RTL, ISA, or runtime evidence disagree on a memory assumption.",
    "evidence": {
      "assumption": "store_latency_cycles",
      "review_question": "Which store_latency_cycles value is authoritative for compiler, simulator, RTL, and runtime evidence?",
      "values": {
        "compiler": 1,
        "rtl": 2,
        "simulator": 2
      }
    },
    "human_review_question": "Which store_latency_cycles value is authoritative for compiler, simulator, RTL, and runtime evidence?",
    "id": "memory_mismatch:store_latency_cycles",
    "permitted_claim": "MEMORY_LAYOUT_REVIEW_TARGET",
    "required_evidence": [
      "ISA memory model",
      "compiler lowering metadata",
      "simulator config",
      "RTL memory map",
      "runtime driver contract"
    ],
    "title": "Memory model mismatch: store_latency_cycles"
  },
  {
    "attention_priority": "P2",
    "category": "simulator_rtl_behavior_mismatch",
    "detail": "store-retirement ordering before HALT is not evidenced in RTL trace",
    "evidence": {
      "gap": {
        "gap": "store-retirement ordering before HALT is not evidenced in RTL trace",
        "mnemonic": "HALT"
      }
    },
    "human_review_question": "What RTL trace or source reference closes this compiler-hardware assumption?",
    "id": "rtl_known_gap:HALT",
    "permitted_claim": "SIMULATOR_RTL_REVIEW_TARGET",
    "required_evidence": [
      "RTL source reference",
      "decode/execute trace",
      "simulator trace comparison"
    ],
    "title": "Known RTL evidence gap for HALT"
  },
  {
    "attention_priority": "P2",
    "category": "runtime_driver_assumption_mismatch",
    "detail": "End-to-end output correctness depends on runtime behavior outside the accelerator execution path.",
    "evidence": {
      "runtime_assumptions": {
        "dma_buffer_alignment_bytes": 16,
        "host_fallback_allowed": true,
        "output_buffer_merge_required": true
      }
    },
    "human_review_question": "Is host fallback output merged, attributed, and excluded from accelerator-only performance claims?",
    "id": "runtime_driver:host_fallback_merge",
    "permitted_claim": "LOWERING_PATH_REVIEW_TARGET",
    "required_evidence": [
      "runtime driver trace",
      "fallback attribution log",
      "output buffer ownership contract"
    ],
    "title": "Runtime must merge host fallback output"
  },
  {
    "attention_priority": "P2",
    "category": "test_coverage_boundary",
    "detail": "The supplied tests do not support broad compiler, simulator/RTL, benchmark, or hardware-readiness claims.",
    "evidence": {
      "test_evidence_summary": {
        "benchmark_repetitions": 1,
        "public_reproduction_steps": false,
        "rtl_tests": [],
        "simulator_tests": [
          "aligned_load_store_smoke"
        ],
        "unit_tests": [
          "asm_emits_expected_mnemonics"
        ]
      }
    },
    "human_review_question": "Which behavior is actually covered by unit, simulator, RTL, and public reproduction evidence?",
    "id": "test_coverage:boundary",
    "permitted_claim": "REVIEW_TARGET",
    "required_evidence": [
      "unit test list",
      "simulator tests",
      "RTL tests",
      "negative tests",
      "public reproduction steps"
    ],
    "title": "Test evidence boundary requires review"
  }
]